1. Field of the Invention
The present invention refers to a device for the correction of the power factor in forced switching power supplies.
2. Description of the Related Art
The use of power factor correction (PFC) devices for the active correction of the power factor (PF) for forced switching power supplies is generally known when used in electronic appliances of common use such as computers, television sets, monitors, etc. and also for the supply of fluorescent lamps, that is of forced switching pre-regulator stages whose task is to absorb current from the mains supply that is almost sinusoidal and is in phase with the mains voltage. Therefore a forced switching power supply of the current type comprises a PFC and a DC-DC converter connected to the output of the PFC.
A forced switching power supply of the traditional type comprises a DC-DC converter and an input stage connected to the distribution mains supply of electrical energy constituted by a full wave diode rectifier bridge and by a capacitor connected immediately downstream so as to produce a direct non-regulated voltage starting from the sinusoidal alternating mains voltage. The capacity of the capacitor is big enough to have a relatively small ripple at its terminals in relation to a continuous level. The rectifier diodes of the bridge, thus, will only conduct for a small portion of each half-cycle of the mains voltage, since its instantaneous value is lower than the voltage on the capacitor for the majority of the cycle. The result is that the current absorbed from the mains will be constituted by a series of narrow pulses whose amplitude is 5-10 times the resulting average value.
This has considerable consequences: the current absorbed from the line has much greater peak values and effectiveness compared with the case of absorption of sinusoidal current, the mains voltage is distorted by effect of the almost simultaneous pulse absorption of all the utilities connected to the mains, in the case of three-phase systems the current in the neutral conductor is greatly increased and there is a low utilization of the energetic potentialities of the electrical energy production system. In fact, the waveform of pulse current is very rich with odd harmonics which, even not contributing to the power given to the load, contribute to increasing the effective current absorbed from the mains and thus to increasing the dissipation of energy.
In quantitative terms all this can be expressed both in power factor (PF) terms, intended as ratio between the real power (that given to the load by the power supply gives plus that dissipated internally in the form of heat) and the apparent power (the product of the effective mains voltage by the effective current absorbed), and in terms of total harmonic distortion (THD), generally intended as percentage ratio between the energy associated with all the harmonics of higher orders and that associated with the fundamental harmonic. Typically, a power supply with capacitive filter has a PF of between 0.4-0.6 and a THD exceeding 100%.
A PFC, positioned between the rectifier bridge and the input of the DC-DC converter, permits an almost sinusoidal current, in phase with the voltage, to be absorbed from the mains, making the PF near 1 and reducing the THD.
FIG. 1 schematically shows a pre-regulator PFC stage comprising a boost converter 20 and a control device 1, in this case the control device L6561 produced by STMicroelectronics S.p.A. The boost converter 20 comprises a full wave diode rectifier bridge 2 having in input a mains voltage Vin, a capacitor C1 (that serves as filter for the high frequency) having a terminal connected to the diode bridge 2 and the other terminal connected to ground, an inductance L connected to a terminal of the capacitor C1, a MOS power transistor M having the drain terminal connected to a terminal of the inductance L downstream thereof and having the source terminal connected to a resistance Rs connected to ground, a diode D having the anode connected to the common terminal of the inductance L and of the transistor M and the cathode connected to a capacitor Co having the other terminal connected to ground. In output the boost converter 20 generates a direct voltage Vout on the capacitor Co exceeding the maximum peak mains voltage, typically 400 V for systems powered with European mains or with universal powering. Such voltage Vout will be the input voltage of the DC-DC converter connected to the PFC.
The control device 1 must keep the output voltage Vout at a constant value by means of a feedback control action. The control device 1 comprises an operational error amplifier 3 suitable for comparing a part of the output voltage Vout, that is the voltage Vr given by Vr=R2×Vout/(R2+R1) (where the resistances R1 and R2 are connected in series to each other and in parallel with the capacitor Co) with a reference voltage Vref, for example of the value of 2.5V, and generates an error signal proportional to their difference. The output voltage Vout presents a ripple at a frequency that is double that of the mains and overlays the continuous value. If however the band amplitude of the error amplifier is considerably reduced (typically lower than 20 Hz) by means of the use of a suitable compensation network comprising at least a capacitor and we assume almost stationary operation, that is with constant effective input voltage and output load, this ripple will be gradually attenuated and the error signal will become constant.
The error signal Se is sent to a multiplier 4 where it is multiplied by a signal Vi given by a part of the mains voltage rectified by the diode bridge 2. At the output of the multiplier 4 a signal Sm will be present and will be a rectified sinusoid whose amplitude will depend, obviously, on the effective mains voltage and on the error signal Se.
The signal Sm is sent to the non-inverting input of a comparator PWM 5 while on the inverting input there is the signal Srs present on the resistance Rs. If the signals Srs and Sm are equal the comparator 5 sends a signal to a control block 6 suitable for driving the transistor M and which, in this case, provides for turning it off. In this manner the output signal Sm of the multiplier determines the peak current of the transistor M and this will thus be enveloped by a rectified sinusoid. A filter disposed at the input of the stage eliminates the switching frequency component and ensures that the current absorbed from the mains has the form of the sinusoidal envelope. The block 6 comprises a zero current detecting block 7 capable of sending a pulse signal to an OR gate 8 whose other input is connected to a starter 10, suitable for sending a signal to the OR gate 8 immediately at the initial time; the output signal S of the OR gate 8 is the set input S of a set-reset flip-flop 11 having another input R which is the output signal of the device 5, and having an output signal Q. The signal Q is sent in input to a driver 12 that controls the turn-on or the turn-off of the transistor M.
The error amplifier 3 can be made in two manners: either as a real voltage amplifier, in which the output voltage is proportional to the difference between the voltages at its input terminals, or as a transconductance amplifier, whose output current is proportional to the difference between the voltages present at the input terminals. It is preferable to use voltage amplifiers as error amplifiers for their greater immunity to noise such as in the device L6561 mentioned.
Considering that in all closed-loop feedback control systems it is necessary to modify the transfer function of the gain of the loop so as to ensure the stability of the loop itself as well as to provide a satisfying dynamic behavior thereof, in the case of the PFCs this is normally done by modifying the frequency reply of the error amplifier. Using a voltage amplifier as error amplifier, the compensation network comprises at least a capacitance C connected in feedback between the output and the inverting input of the amplifier 3.
One of the possible breakdowns in a forced switching power supply with PFC is the breaking of the control loop of the voltage.
The most frequent cause is due to the opening of the resistance R1 of the output divider connected to the high voltage: in this case the system loses the information on the output voltage and the resistance R2 tends to carry the input of the error amplifier towards ground. In this manner the output is unbalanced upwards and therefore the turn-on of the transistor M is commanded for the maximum possible duration. It follows that the output voltage will increase without control, carrying the load fed by the PFC as well as the PFC itself to destruction.
With the error amplifier 3, the presence of the compensation network with the capacitor C positioned between the output and the inverting input limits the latter to the same potential as the other input for the whole time in which the current can flow through the capacitor C, that is until the output of the error amplifier 3 has the possibility of increasing. When the output reaches the upper end of its dynamics or, as is said, the error amplifier 3 is at high saturation, current does not pass any longer in the capacitor and the inverting input can go to zero.
On the market there are integrated PFCs that offer a protection against the opening of the control loop of the voltage. The solution in these PFCs consists of adding another resistive divider (constituted by the resistances R1a and R2a in series to each other) connected to the output of the PFC that permits the reading of the voltage and of using another comparator 28 that has its inverting input connected to the common terminal of the resistances R1a and R2a and the non-inverting input connected to a reference voltage Vth10, as can be seen in FIG. 2. At the moment in which the resistance R1 opens, the voltage on the inverting input of the comparator 28 exceeds the voltage Vth10 and the output 29 of the comparator 28 takes care of turning off the transistor M.